1. Technical Field
The present invention relates to a refresh operation for DRAM (Dynamic Random Access Memory), particularly to a method and apparatus for controlling the refresh period for DRAM during a sleep mode.
2. Prior Art
The DRAM, which is high-speed, high-density and low-bit-cost storage device, is used as a main memory in a computer, for example. To continuously hold data stored in cells of the DRAM, however, the refresh operation must be performed periodically. Because the performance of the refresh operation increases the power consumption necessary to hold data, techniques for reducing the power consumption have been developed.
For example, following techniques are disclosed: a technique for changing a refresh rate according to the temperature (See U.S. Pat. No. 5,278,796); a technique for shifting to a lower and fixed refresh rate in a suspend made (See U.S. Pat. No. 5,465,367); a technique in which cells having an inferior refresh characteristics are replaced with remaining memory cells and the refresh operation for a superior refresh characteristics is performed in a lower refresh rate (See U.S. Pat. No. 5,157,634); a technique for refreshing only memory cells which store effective data (See U.S. Pat. No. 5,469,559).
In addition, there exists a technique with respect to an error correction code used in a memory system. Mainly to prevent the occurrence of errors due to software errors, 1-bit error correctable, 2-bit error correctable, or 4-bit burst error detectable 72-bit code is used in a memory controller of a server, etc. These techniques have a high-speed error correction capability efficient for the software errors, however, in comparison with techniques in the communication or in the HDD (Hard Disk Drive) and etc, they only provide a relatively poor error correction capability. It also has been studied to mount an error correction encoding and decoding circuit on a DRAM chip (See U.S. Pat. Nos. 5,233,614 and 4,249,253, for instance). Furthermore, U.S. Pat. No. 4,617,660 discloses a technique for detecting hardware errors by an error correction circuit and for storing information stored in cells in which the hard ware errors occur in other memory after the correction.
One of references which disclose the correlation of the DRAM refresh with an error correction code technique is U.S. Pat. No. 4,758,992. in this US patent, a technique is disclosed in which because of a countermeasure for software errors, in a dynamic semiconductor storage device including an on-ship error detection/correction circuit, a refresh operation with an operation of the error detection/correction circuit and a refresh operation without the operation of the error detection/correction circuit are made selectable.
However because of a countermeasure for software errors, the error detection/correction circuit has only poor error correction capability, In addition, because it is mounted on the DRAM chip, this technique has defects that it is more expensive than a normal DRAM chip and it is impossible to alter or select the error correction capability in accordance with a request from a system designer, independently of the DRAM chip. Furthermore, this US patent does not specify the time to perform this technique and only discloses the synchronization of the refresh operation and the operation of the error detection/correction.
U.S. Pat. No. 4,935,900 discloses a technique for performing an error detection/correction operation during the refresh operation and for adjusting a clock for the refresh operation in response to the error detection. However, this US patent mentions only the synchronization of the refresh operation and the operation of the error detection/correction and does not specify the time to perform this technique. Because the refresh operation is always synchronized with the error detection/correction operation, even if the power consumption is reduced by extending the refresh period, the power consumption is increased by the error detection/correction operation. On the contrary, because the refresh operation is always synchronized with the error detection/correction, operation, it may assume high-speed but lower error correction capability. Furthermore, because it is mounted on the DRAM chip, this technique has defects that it is more expensive than a normal DRAM chip and it is impossible to alter or select the error correction capability in accordance with a request from a system designer, independently of the DRAM chip. In the whole of this US patent, it is also supposed that because under a consideration that errors will be accumulated so that an error recovery cannot be performed unless the error detection/correction operation is performed every refresh operation because errors occur in a condition in which the refresh period is maximized more frequently than in the normal state, driven by necessity, the error detection/correction operation is performed at each refresh operation. In other words, it is considered that both of extending the refresh period and not performing the error detection/correction operation every refresh operation are contradictory in view of reliability. Therefore, the increase of the power consumption caused by performing the refresh operation and the error detection/correction operation at the same timing becomes a problem. From this viewpoint, mounting the error detection/correction circuit on the DRAM chip is mandatory, however, the standard DRAM chip cannot be used.
Japanese Published Unexamined Patent Publication (PUPA) 04-60988 discloses a technique for measuring a environment condition, and by using the result, reducing the number of the refresh so as not to occur memory errors at the refresh. In addition, it discloses a technique for periodically setting the number of the refresh operation at an appropriate period. However, because it does not disclose any error correction, and discloses the time to start using DRAM is after any error does not occur, and discloses when the number of the refresh operation is periodically set at an appropriate period, data stored in the DRAM is copied to an external storage device, it is understood that the time to reduce the number of refresh operations first time in this publication is immediately after the computer is powered on. Therefore, if meaningful information is stored in the DRAM it is impossible to simply apply this technique disclosed in this publication. Furthermore, because when the number of the refresh operation is periodically set at an appropriate period, data stored in the DRAM is copied to an external storage device, extra power is consumed.
IBM Technical Disclosure Bulletin Vol. 34 No. 10B pp 217-218, March 1992 (hereinafter called TDB1) discloses a technique for performing a test at the power-on of a system, and setting a refresh period which is longest within a range that errors is correctable by the error correction code. However, because the test requires a test pattern stored in SPAM (Static Random Access Memory), extra hardware is needed. Furthermore, because the refresh period set based on the test at the power-on, the technique disclosed in the TDB1 cannot be performed if the meaningful information is stored in the DRAM.
Further, still IBM Technical Disclosure Bulletin Vol. 40 No. 6, pp 31-32, June 1997 (hereinafter called TDB2) discloses the following:
to realize a high-density and low-cost battery-backup memory system, the adaptive DRAM refresh scheme with on-chip error correction/checking and compression circuits is adopted, and in a suspend mode, following operations are performed: (1) The on-chip logic circuitry performs error coding (both checking and correction) and compression of the stored data. This operation can be performed either once for the entire memory or many times after dividing the memory into multiple segments. (2) The timer triggers the refresh operation for a certain segment with only error checking. If no error was found, the next refresh for that segment will be performed with a prolong refresh cycle. (3) A SRAM is necessary. This is for performing the interval of the refresh cycle for different segments as well as for storing the temporary data during the error coding and compression operation.
The technique disclosed in TDB2 has following problems. That is, since, as well as some conventional technique, the error correction/checking circuit and the compression circuit are mounted on the DRAM chip, it is more expensive than a normal DRAM chip and it is also impossible to alter or select the error correction capability. In addition, because for each refresh, only error checking is performed at the same time, and only a case where there is no error causes the refresh cycle to be prolonged, for extending the refresh period efficiently, it is necessary to divide the DRAM into a plurality of segments and to change the refresh cycle for each segment. Furthermore, for reliably storing the refresh cycle for each segment, the SRAM is required, then the cost further increases.
By using the above described conventional technique, it is difficult to obtain a longer refresh period for DRAM which stores meaningful data, and whereby to provide highly reliable data storage and low power consumption. For example, those are not appropriate for following applications.
(1) in a server or a workstation, for storing memory contents by using a smaller battery capacity.
(2) in a PC, for storing memory contents in DRAM after the transition to the sleep state (In this application, the sleep state is widely defined as a state in which there is no read access or write access to a memory device from outside, which requires the refresh operation to continuously store data, such as DRAM.) By holding contents of DRAM with a smaller power even after the main power is turned off, it is enabled that the system quickly wakes up when the main power is turned on. As a result, an operation that the contents in the main memory is stored into a hard disk becomes unnecessary.
(3) in a network computer or a small personal information assistance, for replacing a non-volatile memory, such as a flash memory.
(4) in a small memory card for a digital camera etc., for replacing a non-volatile memory, such as a flash memory.
As described above, using the conventional technique it is difficult to adequately extend the refresh period for the DRAM in storing meaningful data.
It is, therefore, one object of the present invention to adequately extend the refresh period for the DRAM storing meaningful data.
It is another object of the present invention to adequately extend, during a sleep mode, the refresh period for a memory device, such as the DRAM, which stores meaningful data and for which a refresh operation is required to maintain data.
It is an additional object of the present invention to optimize, during a sleep mode, the refresh period for a memory device, such as the DRAM, which stores meaningful data and for which a refresh operation is required to maintain data.
It is a further object of the present invention to provide a memory system that optimizes, during a sleep mode, the refresh period for a memory device, such as the DRAM, which stores meaningful data and for which a refresh operation is required to maintain data, and that can cope with environmental changes in the vicinity of the memory device.
It is still another object of the present invention to provide a reliable memory system having a highly effective error correction function or a technique for replacing with a substitute area a portion of a memory where errors tend to occur.
It is a still further object of the present invention to provide a simple computer at a lower cost by using standard DRAM chips as to the extent as possible.